The Use of Caching in Decoupled Multiprocessors with Shared Memory

In the following we evaluate the costs and beneets of using a cache memory with a decoupled architecture supporting shared memory in both the uniprocessor and multiprocessor cases. Firstly we identify the performance bottleneck of such architectures, which we deene as Loss of Decoupling costs. We show that in both uniprocessors and multiprocessor machines with high latency such costs can greatly eeect performance. We then assess the ability of cache to reduce loss of decoupling costs in both uniprocessors and multiprocessors. Through use of graphical tools we provide an intuition as to the behaviour of such decoupled machines. In multiprocessors we deene the target model of shared memory and introduce various coherency schemes to implement the model. Each coherency scheme is then evaluated experimentally. We show that hardware coherence schemes can improve the performance of such architectures, though the relationship between hit rate and performance is substantially diierent than in the non-decoupled case. Our results are based on discrete-event simulations which take as input address traces from various scientiic applications.